Method for isolation of circuit regions in monolithic integrated circuit structure

ABSTRACT

POLYCRYSTALLINE SILICON HAVING A NEEDLE-LIKE ORIENTED GRAIN STRUCTURE IS FOUND TO HAVE ANISOTROPIC ELECTRICAL AND THERMAL PROPERTIES. A MONOLITHIS INTEGRATED CIRCUIT STRUCTURE HAVING A PLURALITY OF MONOCRYSTALLINE SILICON ISLANDS IS FABRICATED IN A POLYCRYSTALLINE SILICON MATRIX HAVING SUCH A GRAIN STRUCTURE, WITH THE GRAIN DIRECTION ORIENTED TO PROVIDE MAXIMUM ELECTRICAL RESISTIVITY BETWEEN THE MONOCRYSATLLINE ISLANDS, AND MAXIMUM THERMAL CONDUCTIVITY TOWARD A HEADER OR OTHER HEAT SINK IN ONE EMBODIMENT, THE MONOCRYSTALLINE ISLANDS AND POLYCRYSTALLINE MATRIX ARE GROWN BY VAPOR DEPOSITION OF SILICON ON A MONOCRYSTALLINE SUBSTRATE PROVIDED WITH A SUITABLE MASKING PATTERN, WHEREBY THE POLYCRYSTALLINE MATERIAL GROWS ON THE MASK CONCURRENTLY WITH THE GROWTH OF MONOCRYSTALLINE SILICON ON THE UNMASKED AREAS OF THE SUBSTRATE.

Scpt. 10, 1974 K. E. BEAN ETAL 3,834,958

METHOD FOR ISOLATION OF CIRCUIT REGIONS IN MONOLITHIC INTEGRATED CIRCUITSTRUCTURE Criginal Filed Feb '17, 1969 2 Sh Fig.2

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ME'IHOD FOR LATION 0F CIRCUIT REGIONS IN MONOLITHIC INTEGRATED CIRCUITSTRUCTURE Original Filed Feb 17, 1969 2 SheetsSheet 2- Fig; 6

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United States Patent METHOD FOR ISOLATION OF CIRCUIT REGIONS lNMONOLITHIC INTEGRATED CIRCUIT STRUCTURE Kenneth E. Bean, Richardson, andPaul S. Gleirn, Dallas,

Tex., assiguors to Texas Instruments Incorporated, Dallas, Tex.

Original application Feb. 17, 1969, Ser. No. 799,721, now Patent No.3,624,467. Divided and this application Dec. 17, 1970, Ser. No. 99,289

Int. Cl. H011 7/50 US. Cl. 156-8 4 Claims ABSTRACT OF THE DISCLOSUREPolycrystalline silicon having a needle-like oriented grain structure isfound to have anisotropic electrical and thermal properties. Amonolithic integrated circuit structure having a plurality ofmonocrystalline silicon islands is fabricated in a polycrystallinesilicon matrix having such a grain structure, with the grain directionoriented to provide maximum electrical resistivity between themonocrystalline islands, and maximum thermal conductivity toward aheader or other heat sink. In one embodiment, the monocrystallineislands and polycrystalline matrix are grown by vapor deposition ofsilicon on a monocrystalline substrate provided with a suitable maskingpattern, whereby the polycrystalline material grows on the maskconcurrently with the growth of monocrystalline silicon on the unmaskedareas of the substrate.

This application is a division of application Ser. No. 799,721, filedFeb. 17, 1969, now U.S. Pat. 3,624,467 issued Nov. 30, 1971.

This invention relates to a monolithic integrated circuit structureincluding an array of isolated monocrystalline silicon islands, and to amethod for its fabrication. More particularly, the invention relates tosuch a structure wherein dielectric isolation of the monocrystallineislands is provided by a polycrystalline silicon matrix having anoriented needle-like grain structure characterized by anisotropicelectrical and thermal properties.

Monolithic integrated circuit structures comprising an array ofmonocrystalline semiconductor regions electrically isolated by one ormore discrete layers of a dielectric material represent a substantialadvance in many respects over the more common use of p-n junctionisolation to provide electrical separation between circuit elements.Perhaps the most significant advantage of the so-called multiphasemonolithic integrated circuit is the elimination of parasiticcapacitance between the substrate and active elements of the circuit.Also eliminated in the multiphase structure is the parasitic transistorconsisting of the base-collector-substrate combination, characteristicof the conventional monolithic circuit.

Polycrystalline silicon has been frequently suggested as a matrixmaterial to be used in the fabrication of multiphase monolithicintegrated circuits because it has a coefficient of thermal expansionsubstantially equal to that of the monocrystalline silicon regions.However, since polycrystalline silicon normally does not have asufiicient electrical resistivity to provide the required isolation, ithas previously been necessary to provide a continuous layer of silicondioxide or other dielectric material between the monocrystalline regionsand the polycrystalline silicon substrate of such structures. It has nowbeen discovered that when polycrystalline silicon is grown in such amanner as to provide an oriented needle-like grain structure, thematerial has anisotropic electrical and thermal properties.Specifically, maximum electrical and thermal conductivity are observedin the direction of the grain, and a minimum electrical and thermalconductivity are 3,834,958 Patented Sept. 10, 1974 observed in adirection perpendicular to the .grain structure. Measurements parallelto the grain structure have indicated a thermal conductivity of about0.9 watts per cm. per degree centigrade at about 0, whereasperpendicular to the grain structure a thermal conductivity of about 0.6watts per cm. per degree centigrade was observed. An electricalresistivity of 5.2 10 ohm-ems. was observed parallel to the graindirection, and 5.9)(10 ohms-ems. perpendicular to the grain direction.These properties have been found particularly advantageous in theconstruction of a multiphase monolithic integrated circuit structure, aswill be apparent from a consideration of the specific embodiments of theinvention described below.

It is an object of the invention to provide an improved monolithicintegrated circuit structure. More particularly, it is an object of theinvention to provide a monolithic integrated circuit structure having aplurality of electrically isolated monocrystalline silicon islandsembedded in a polycrystalline silicon matrix, characterized by improveddissipation of heat generated in the monocrystalline islands, andincreased packing density of circuit elements.

It is a further object of the invention to provide an improved methodfor the fabrication of a monolithic integrated circuit structure and, inone aspect, to provide a method for the fabrication of an all-siliconstructure, characterized by monocrystalline silicon islands embedded ina polycrystalline silicon matrix. It is a further object of theinvention to provide a method involving the concurrent growth ofmonocrystalline and polycrystalline silicon for the fabrication of amonolithic structure wherein monocrystalline islands are surrounded by apolycrystalline matrix having an oriented needle-like grain structure.

The invention is embodied in a monolithic integrated circuit structureincluding a polycrystalline silicon matrix having an orientedneedle-like grain structure, and a plurality of monocrystalline siliconislands contained in the matrix. Each monocrystalline island includes asubstantially planar surface oriented perpendicular to the grain of thepolycrystalline matrix. Such orientation takes advantage of theanisotropic electrical and thermal properties of the polycrystallinematrix. That is, the electrical resistivity between islands is maximizedsince that direction is perpendicular to the matrix grain, whereasdissipation of heat from the monocrystalline islands is optimized in adirection parallel with the grain structure of the matrix. The completedstructure includes at least one circuit element within each of aselected number of monocrystalline islands, in combination with meansfor providing suitable electrical interconnection of the circuitelements. Actually, it will be apparent that each island may include acircuit element. Frequently, however, some of the islands are not neededto complete a given circuit design, and would therefore not be used.

The invention is further embodied in a monolithic integrated circuitstructure including a polycrystalline silicon matrix having asubstantially planar surface and a needlelike grain structure orientedsubstantially perpendicular to the planar surface. An array ofmonocrystalline silicon islands are located in the matrix, each islandhaving a. surface lying substantially in the same plane as said matrixsurface. As noted above, the completed structure includes at least onecircuit element within each of selected monocrystalline islands, incombination with means for electrically interconnecting the elements. Inaccordance with a preferred embodiment, each island forms amonocrystalline-polycrystalline interface with the matrix. In such astructure, the usual layer of silicon dioxide is eliminated, therebyfacilitating the dissipation of heat from each island into thepolycrystalline matrix, and subsequently to a header or other heat sink.

The invention is also embodied in a method for the fabrication of amonolithic integrated circuit structure,

beginning with the steps of providing .a monocrystalline silicon bodyhaving a substantially planar surface, and forming on said surface asuitable masking layer patterned to provide therein a plurality ofspaced apart openings. The masked silicon body is exposed to anatmosphere containing a vaporous or gaseous silicon compound, atepitaxial growth conditions, whereby monocrystalline silicon islands areformed on the exposed portions of the silicon surface, surrounded bypolycrystalline silicon concurrently deposited on the mask. Preferably,the concurrent growth of monocrystalline and polycrystalline silicon iscontinued until a thickness is achieved sufficient to provide thenecessary structural strength of the vapor-deposited layer, aftersubsequent removal of the original monocrystalline substrate. At leastone circuit element is formed in each of selected monocrystallineislands, and the elements are suitably interconnected electrically. Theformation of circuit components and/or the step of electricallyinterconnecting said components may be carried out either before orafter the removal of the original monocrystalline silicon substrate.

In accordance with a more specific embodiment of the above method, theplanar surface of the monocrystalline silicon body initially providedhas a (110) crystallographic orientation. By providing such orientation,the geometry of the masking layer is preserved or transferred throughthe entire thickness of the deposited silicon. That is, the interfacebetween the deposited monocrystalline and polycrystalline siliconremains perpendicular to the substrate surface throughout the entireoperation. The ability to so maintain a perpendicular interface permitthe deposited material to be grown as thick as desired without departingsubstantially from the geometric pattern initially provided in themasking layer.

The geometry of the interface between monocrystalline andpolycrystalline silicon is improved still further, in accordance with amore specific embodiment of the method, by patterning the masking layerto provide openings having at least one side oriented parallel to theintersection of a (111) plane with the (110) plane of the substratesurface. Preferably the mask windows are parallelograms having each sideoriented parallel to an intersection of a (111) plane with the substratesurface. The controlled deposition of silicon on such a masked substrateproceeds smoothly to provide substantially planar walls between eachmonocrystalline island and the surrounding polycrystalline matrix.

In an alternate embodiment, the concurrent growth of monocrystalline andpolycrystalline silicon is interrupted when a thickness is achievedcorresponding substantially to the thickness which a monocrystallineisland must have in order to accommodate whatever circuit elements areto be formed therein. Then the composite layer of monocrystalline andpolycrystalline silicon is covered by a suitable dielectric material,followed by the deposition of additional polycrystalline silicon on thedielectric layer, followed by removal of the original silicon substrate.

In another embodiment, the method of the invention begins with the stepsof providing a monocrystalline silicon body having a substantiallyplanar surface, and selectively etching said surface to form is networkof channels therein and a plurality of raised, mesa-like regions.Polycrystalline silicon having a needle-like grain structure orientedperpendicular to the substrate surface is then deposited on the etchedsurface. Monocrystalline silicon is removed from the reverse side of thesubstrate until a portion of the channel network becomes exposed,thereby isolating a plurality of monocrystalline regions surrounded bypolycrystalline silicon, each monocrystalline region having a surfaceperpendicular to the grain structure of said polycrystalline matrix. Thestructure is then completed by forming at least one circuit component ineach of selected monocrystalline regions and suitably interconnectingthe components electrically.

Polycrystalline silicon is generally known to have a grain structure;and an elongated or needle-like grain shape has been previouslyobserved. But a needle-like grain structure wherein the longitudinalaxes of the individual grains point randomly in all directions is notoriented. Thus, at least for purposes of this disclosure, the termoriented needle-like grain structure refers to a grain structure whereinthe majority of the individual grains have longitudinal axes arranged insome orderly pattern. Usually, in accordance with the invention, the

, grain direction is substantially perpendicular to the surface on whichthe polycrystalline silicon is being grown. Accordingly for depositionon a planar surface, the oriented grains all point in the samedirection, i.e., substantially parallel to each other.

FIGS. 1, 2 and 3 are cross-sectional views of a semiconductor wafer,illustrating a sequence of intermediate stages carried out in thepractice of one embodiment of the invention.

FIG. 4 is a cross-sectional view of a structure completed in accordancewith the invention, representing the product of the method illustratedby FIGS. 1, 2 and 3.

FIGS. 5 and 6 are cross-sectional views of a semicon ductor wafer,illustrating a sequence of steps carried out in accordance with a secondembodiment of the invention. FIG. 7 is a cross-sectional view of acompleted structure made in accordance with the method illustrated byFIGS. 5 and 6.

FIGS. 8 and 9 are cross-sectional views of a semiconductor wafer,illustrating a sequence of steps performed in accordance with a thirdembodiment of the invention. FIG. 10 is a cross-sectional view of acompleted structure prepared by the method illustrated in FIGS. 8 and 9.

FIGURES 1-4 Monocrystalline silicon wafer 11, having a diameter of about1 inch and a thickness of about 8 mils, is prepared from knowntechniques, or is obtained from known sources. Preferably, wafer 11 hasa crystallographic orientation to provide a working surface having a(110) orientation. Layer 12 of silicon dioxide is formed on the surfaceof Wafer 11 by any suitable technique including, for example, thermaloxidation or the vapor-deposition of silicon dioxide from an organicsilicon compound in an oxidizing atmosphere, at deposition conditions.Layer 12 has a thickness of to 100,000 angstroms and preferably about10,000 angstroms. Masking layer 12 is then patterned to provide windows13, using known photolithographic techniques. The size and arrangementof windows 13 correspond to the desired size and arrangement ofmonocrystalline silicon islands to be isolated in a ploycrystallinesilicon matrix. Preferably the masking pattern includes parallelogramwindows, each side of which is parallel to the intersection of a (111)plane with the surface of water 11.

The structure of FIG. 1 is then subjected to suitable conditions for theconcurrent growth of monocrystalline silicon in the windowed areas andthe growth of polycrystalline silicon on mask patern 12 to provide thestructure as illustrated by FIG. 2. The preferred conditions for silicongrowth include a molar ratio of silicon halide (or silicon hydride) tohydrogen of 1% to 4% and preferably about 23%. Substrate temperature ismaintained in the range of 900-1350 C., and preferably about 11S0-1300C. These conditions are suitable, not only because high qualitymonocrystalline silicon is deposited in Windowed areas 13, but primarilydue to the fact that these conditions ensure the formation of anoriented needle-like grain structure in polycrystalline silicon region15. The resulting grain structure is perpendicular to the surface ofmasking layer 12. Such orientation is preferred because the grainstructure exhibits a maximum electrical resistivity perpendicular to thegrain direction,

thereby providing a maximum electrical isolation of monocrystallineislands 14.

A specific example of the process is carried out in a vertical reactorsystem characterized by an indirect flow pattern for reactor gases. Sucha system is available from Ecco High Frequency, Inc. of North Bergen,N]. In a ten-slice reactor (1.5 in. diameter slices) having a dome sizeof about 9%" LD. and a 7%" susceptor, suitable results are obtainedusing a temperature of 1150 C. and a total flow rate of about 40 litersper minute, consisting of 3% trichlorosilane and 97% hydrogen.

The original substrate 11 and masking pattern 12 are then removed bylapping, polishing and/or etching techniques to produce a structure asshown in FIG. 3 which consists essentially of monocrystalline islands 14surrounded by polycrystalline silicon matrix 15.

As shown in FIG. 4, the structure of FIG. 3 is completcd by providingoxide layer 16, to be used as a diffusion mask. in the formation ofdiffused regions 17, 18, 19 and 20yvhich represent suitable active and/or passive circuit components fabricated within island 14, includingdiodes,transistors, resistors, etc., for example. The fabrication ofsuch diffused regions or other active or passive components is carriedout in accordance with known techniques which need not be disclosed indetail for the purpose of understanding the present invention. Suitableohmic' contacts 21-27 are then provided, also in accordance with knowntechniques which need not be described in detail for purposes of thepresent disclosure. The resulting integrated circuit structurerepresents an advance in the art, primarily due to the increased rate ofthermal dissipation made possible by elimination of the usual dielectriclayer interposed between such a polycrystalline matrix and each of themonocrystalline islands. The present approach also reduces the cost offabrication and increases the packing density of circuit elements. Stillfurther, this embodiment permits selective gold diffusion from thebackside of the wafer to provide separate control of minority carrierlifetimes within each island. The back side of the wafer is alsoavailable for ohmic contacts, such as to a collector region, forexample.

In an alternate embodiment, the silicon deposited on the structure ofFIG. 1 is doped to provide the opposite conductivity type with respectto substrate 11. That is, a p-n junction is formed epitaxially at thelevel of windows 13. Thus, a structure is provided essentially the sameas shown in FIG. 2, but with p-n junction isolation of islands 14 in thevertical direction, and matrix isolation horizontally. Accordingly,device fabrication is then possible as the next step, without the needto remove any of the original substrate.

FIGS. 5-7

In accordance with a further embodiment, the sequence of FIGS. l-4 isslightly altered, first by limiting the thickness of both themonocrystalline and polycrystalline regions deposited upon the maskedwafer structure. As shown in FIG. 5, the polycrystalline silicon areas31 and monocrystalline regions 32 are grown to a thickness of only 1-2mils, which thickness is insufficient to avoid breakage in the eventthat the original substrate 11 were to be removed as in the previousembodiment. Accordingly, in order to provide such structural strength,oxide layer 33 or other dielectric material is deposited across thecomposite surface of the deposited regions, followed by the continuedgrowth of polycrystalline silicon to provide a structural base 34.Polycrystalline silicon is employed to provide base 34 primarily forconvenience; other materials can readily be substituted therefor.

Next, the original substrate 11 is removed, as before, by knowntechniques including for example, a combination of lapping, polishingand etching procedures to produce a structure essentially as shown inFIG. 6. Oxide layer 35 is then provided on the lapped and polishedcomposite surface of regions 31 and 32.

The structure is completed by the formation of diffused regions 3639 inaccordance with known techniques to provide suitable circuit elementswithin the monocrystalline islands. Thereafter, suitable ohmic contacts40-46 are provided, also in accordance with known techniques, toestablish the necessary means for interconnection of the circuitcomponents. A more detailed description of component fabrication andohmic contact placement is unnecessary for purposes of the presentdisclosure.

Monocrystalline silicon wafer 51, having n-type conductivity, aresistivity of about 0.4 to 0.6 ohm-cm, a thickness of about 8 mils, anda diameter of about 1 inch, is prepared by known techniques or obtainedfrom known sources. A diffused or epitaxially grown region 52 having thesame conductivity type but a substantially lower resistivity is providedby known techniques. Region 52 has a thickness, for example, of 2 to 6microns, preferably about 4 microns.

Next, using known selective etching techniques, a channel networkpattern 53 is provided in the surface of wafer 51. The depth andgeometric pattern of channel network 53 is selected to provide an arrayof raised, mesa-like regions corresponding in size and thickness to thedesired dimensions of monocrystalline silicon islands to be provided inthe completed structure. Polycrystalline silicon layer 54 is thendeposited on the channeled surface of wafer 51. Since thepolycrystalline silicon is deposited directly upon a monocrystallinesilicon surface, process conditions must be selected to avoidmonocrystalline epitaxial growth. For example, the growth of layer 54may be initiated at a temperature which is too low for monocrystallinegrowth, resulting initially in the deposition of an amorphous siliconlayer (not shown) having a thickness just sufficient to interrupt themonocrystalline lattice. Thereafter, conditions may be modified togenerate an optimum growth of polycrystalline silicon. Preferably, thepreviously mentioned conditions for forming an oriented needle-likegrain structure are employed. Polycrystalline region 54 is grown to athickness just sufiicient to provide the necessary structural integrityrequired for subsequent handling.

Next, as shown in FIG. 10, a portion of the original wafer 51 is removedby known lapping, polishing and/or etching techniques until channelpattern 53 is clearly exposed, thereby isolating an array ofmonocrystalline regions in which circuit components are to befabricated. Oxide layer 55 is then deposited by known techniques toserve as the diffusion mask and passivation layer. Next, in accordancewith known techniques, diffused regions 56-61 are formed in therespective monocrystalline islands to provide suitable circuitcomponents. Ohmic contacts 6271 are then provided to the respectivecomponent regions using known techniques, thereby providing suitablemeans for electrical interconnection of the respective circuitcomponents.

In the illustrated embodiment, region 52 is formed prior to the etchingof channel network 53. However, for some applications it is preferred toetch first and then form an N+ layer which follows the contour of thechannels. This provides a so-called wraparound path of low resistivityin the completed structure, which facilitates surface collectorcontacts.

For each of the specific embodiments described, a direct interfacing ofthe monocrystalline islands with the polycrystalline matrix is shown.However, it is also within the scope of the invention, in its broadestaspects, to interpose a thin layer of SiO or other dielectric betweenthe islands and the matrix. The combination of increased electricalresistivity in the matrix, plus the added electrical isolation of anexceptionally thin SiO layer provides an advantageous structure, sincethe SiO layer can be thin enough to permit adequate thermal dissipation,without risking any serious failure due to electrical leaks in the eventof pinholes or other discontinuities in the SiO What is claimed is 1. Ina method for electrically isolating islands of monocrystalline siliconin the fabrication of a monolithic integrated circuit, said methodcomprising:

forming a patterned masking layer on a substantially planar surface of amonocrystalline silicon body having a (110) crystallographic orientationwherein a plurality of spaced apart openings are provided in thepatterned masking layer to expose separate portions of the planarsurface of said monocrystalline silicon body with the openings beingarranged to have respective sides oriented parallel to the intersectionof a (111) plane with the exposed separate portions of the planarsurface of said monocrystalline silicon body,

exposing the masked monocrystalline silicon body to a silicon-containingatmosphere under conditions favoring the epitaxial growth of silicon,and

forming respective upstanding monocrystalline silicon growths on theexposed separate portions of said planar surface of said monocrystallinesilicon body While simultaneously forming an upstanding polycrystallinesilicon growth upon the masking layer as a needle-like grain structureoriented perpendicular to the surface of the masking layer to define apolycrystalline silicon matrix separating the monocrystalline silicongrowths from each other in response to the exposure of the maskedmonocrystalline silicon body to the silicon-containing atmosphere.

2. A method as set forth in claim 1, wherein said monocrystallinesilicon body is of one conductivity type, and wherein the maskedmonocrystalline silicon body of said one conductivity type is exposed toa silicon-containing atmosphere including a dopant material of a kindproducing the opposite conductivity in silicon under conditions favoringthe epitaxial growth of silicon, whereby the respective upstandingmonocrystalline silicon growths are formed of opposite conductivitytypeto said one conductivity type of said monocrystalline silicon body toprovide respective P-N junctions between each of said nionocrystallinesilicon growths of opposite conductivity ype and said monocrystallinesilicon body of said one con: ductivity type. i

3. A method as set forth in claim 1, further including 7 forming aninsulation layer covering the monocrystalline silicon growths and thepolycrystalline silicon matrix,

forming a layer of polycrystalline silicon covering said insulationlayer to provide a structural base of poly: crystalline silicon, andremoving the original monocry'st'alline silicon body and the patternedmasking layer provided on the planar surface thereof, thereby forming aplurality of islands of monocrystalline silicon from the monocrystallinesilicon growths respectively separated from each other by thepolycrysalline silicon matrix. 4. A method as set forth in claim 3,further including forming a second insulation layer covering the monocrystalline silicon islands and the polycrystalline silicon matrixseparating said monocrystalline silicon islands from each other.

References Cited Mitari et al.- 29577 WILLIAM A. POWELL, PrimaryExaminer US. Cl. X.R. 156--l7

